1. Technical Field of the Invention
This disclosure relates to a semiconductor device and a fabrication method thereof and more particularly to a semiconductor device with a gate spacer having a positive slope in the edge thereof to prevent a bridge from generating due to polysilicon residues, and a fabrication method thereof.
2. Description of the Related Art
Generally, as the design rule of a semiconductor device is reduced, so is the space between gates. Therefore, a gap-fill process of an inter-insulation layer is an important issue. There are two conventional fabrication methods used to form an inter-insulation layer in semiconductor technology. One is to deposit an oxide layer between gates before depositing a polysilicon layer to form a contact pad. The other is to deposit a polysilicon layer for a contact pad between gates, which has a better gap-fill characteristic than an oxide layer, to etch a portion of the polysilicon layer, and to deposit an oxide layer in the etched portion of the polysilicon layer.
In the former fabrication method, a void is generated when the oxide layer is deposited in the narrow gap between the gates, and a bridge-fail is generated due to the void. Because the latter fabrication method first deposits a polysilicon layer that has an excellent gap-fill characteristic, and then deposits the oxide layer in the etched portion of the polysilicon layer, a void is not generated. Therefore, a bridge-fail due to the void does not happen.
FIG. 1A to FIG. 1E are cross sectional diagrams illustrating a conventional fabrication method of a semiconductor device.
Referring to FIG. 1A, a gate insulation layer 110 is grown on a silicon substrate 100. On the gate insulation layer 110, a polysilicon layer 121, a tungsten W layer 123, and a gate capping layer 125 are sequentially deposited. A gate 120 is formed by patterning the gate capping layer 125, the tungsten layer 123, and the polysilicon layer 121.
Next, to prevent an electric field concentration at the edge of the polysilicon layer and to protect a tungsten layer 123 of the gate 120, a gate poly oxidation process is performed to grow an oxide layer (not shown) on the silicon substrate 100 including the gate 120.
Referring to FIG. 1B, a middle temperature oxide (MTO) layer 131 is formed on the silicon substrate 100, and a nitride layer 133 for a gate spacer is deposited on the silicon substrate 100. Sequentially, the nitride layer 133 and the oxide layer 131 are etched to form a gate spacer 130 on the sidewall of the gate 120. A cleaning process is performed. The cleaning process uses a cleaning solution, such as the standard cleaning 1 (SC1) solution composed of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and de-ionized (DI) water in a 1:4:20 volume ratio.
Referring to FIG. 1C, a polysilicon layer 140 for a contact pad is deposited on the silicon substrate 100 to fill the gap between gates, and planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the polysilicon layer 140 to isolate a node.
Referring to FIG. 1D and FIG. 1E, the polysilicon layer 140 is etched to form an opening 150, and an inter-insulation layer 160, such as a high density plasma (HDP) oxide layer, is deposited to fill the opening 150. Next, a CMP process is performed to planarize the inter-insulation layer 160.
As described in the above statements, the fabrication method according to the conventional semiconductor device first performs a gap-fill process of a polysilicon layer and then deposits an inter-insulation layer in the opening. Therefore, even though a void is generated in the inter-insulation layer, a bridge-fail due to the void in the inter-insulation layer is prevented.
However, when the cleaning process is performed after forming the gate spacer 130, a portion of the MTO layer 131 and the gate insulation layer 110 underneath the nitride layer 133 is etched to generate an undercut portion 170 in the edge of the gate spacer 130, as shown in FIG. 1B. Therefore, when the polysilicon layer 140 is etched to form the opening 150, the polysilicon layer 140 is not removed completely, and a polysilicon residue 175 remains in the undercut portion 170 in the edge “A” of the gate spacer 130, as shown in FIG. 1D. As a result, the polysilicon residue 175 causes a bridge-fail.
Embodiments of the invention address this and other problems in the conventional art.